NXP Semiconductors /LPC15xx /DMA /CFG8

Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.

0 (DISABLED): Disabled. Peripheral DMA requests are disabled.

1 (ENABLED): Enabled. Peripheral DMA requests are enabled.

Hardware Triggering Enable for this channel.

0 (DISABLED): Disabled. Hardware triggering is not used.

1 (ENABLED): Enabled. Use hardware triggering.

Reserved. Read value is undefined, only zero should be written.

Trigger Polarity. Selects the polarity of a hardware trigger for this channel.

0 (ACTIVE_LOW__FALLING): Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.

1 (ACTIVE_HIGH__RISING): Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.

Trigger Type. Selects hardware trigger as edge triggered or level triggered.

0 (EDGE): Edge. Hardware trigger is edge triggered.

1 (LEVEL): Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel.

Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.

0 (SINGLE_TRANSFER): Single transfer. Hardware trigger causes a single transfer.

1 (BURST_TRANSFER): Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.

Reserved. Read value is undefined, only zero should be written.

Burst Power is used in two ways. It always selects the address wrap size when SrcBurstWrap and/or DstBurstWrap is modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). … 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported.

Reserved. Read value is undefined, only zero should be written.

Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.

0 (DISABLED): Disabled. Source burst wrapping is not enabled for this DMA channel.

1 (ENABLED): Enabled. Source burst wrapping is enabled for this DMA channel.

Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.

0 (DISABLED): Disabled. Destination burst wrapping is not enabled for this DMA channel.

1 (ENABLED): Enabled. Destination burst wrapping is enabled for this DMA channel.

Priority of this channel when multiple DMA requests are pending. This description reflects a 3-bit priority field giving 8 priority levels. A specific instance of the SDMA might have anywhere from 2 to 16 priority levels (1 to 4 bits for the CH_PRIORITY field). 0x0 = highest priority. 0x7 = lowest priority.

Reserved. Read value is undefined, only zero should be written.